Analog-to-digital converters are devices, ranging from monolithic integrated circuits to high-performance hybrid circuits and modules which convert analog data or signals (hereinafter collectively identified as "data") into an equivalent digital form. The analog data is most often, but certainly not always, a voltage.
The key characteristics of ADC's which distinguish one from another include absolute and relative accuracy, linearity, presence or absence of missing codes, resolution, conversion speed, stability and price. Other aspects open to choice include input signal ranges, digital output codes, interfacing techniques, presence of on-board multiplexing, signal conditioning, and memory.
There are several types of ADC's. The most common type is probably the successive approximation converter, which often represents an acceptable compromise between speed and accuracy. Other popular alternatives are based upon integrating techniques (such as the dual-ramp, quad-slope and voltage-to-frequency converters), counting and tracking techniques (e.g., counter-comparator converters), converters employing digitally corrected subranging techniques and "flash" converters. The latter are a particularly high-speed design and are therefore useful in video signal processing and other high-frequency signal conversion situations.
The hallmark of flash converters is parallel operation, which provides the very high-speed characteristics for which this type of converter is known. FIG. 1 shows a basic prior art three-bit flash converter 10. It has 2.sup.n -1 latched comparators, biased one LSB apart, starting with +1/2 LSB, where "n" is the number of bits. A resistive voltage divider, indicated generally at 12, operating off of a reference voltage source connected to terminal 14 but not shown, provides the reference voltages for the comparators 16-1 through 16-7. The reference voltage for each comparator 16-i is one least significant bit (LSB) higher than the reference voltage for the comparator 16-(i-1) immediately below it. The outputs of the comparators collectively provide a "thermometer code" which corresponds to the magnitude of the analog input signal. The comparator outputs are then provided, from pairs of electrically adjacent comparators, to gates 22, 24, 26, 28 and 32; the outputs from these gates, with the output from the "topmost" comparator 16-7 forms a "1 of N" selection code. The "1 of N" code is applied to an encoder 34. Though shown as an OR array using OR gates 35A, 35B and 35C to generate a three-bit binary code output, the encoder 34 could assume other common forms. The encoder 34 is sometimes referred to as a read-only memory (ROM).
Flash decoders having eight-bit resolution require 255 comparators and comparable amounts of decoding logic. It can thus be readily seen that these converters are often relatively impractical to construct from discrete comparators and logic elements, due to power, size, wiring and cost considerations. Monolithic devices have been developed, however, for flash converters ranging from 4 to 10 bits of resolution.
The obvious advantage of the flash converter of FIG. 1 is that conversion occurs in parallel, with speed limited only by the switching time of the comparators and gates. As the input changes, the output code changes. Thus, this is the fastest (or at least one of the fastest) approaches to conversion. Unfortunately, the number of elements increases geometrically with resolution.
Parallel flash conversion is often combined with digitally corrected subranging to strike a compromise that gives better resolution than the parallel approach with less complexity, but still maintaining a speed improvement over the successive approximation approach.
Additionally, although the comparator latches essentially perform a track and hold function, high-speed, high-resolution systems often employ an external track and hold element for best performance.
A functional block diagram for a typical prior art 6-bit flash converter is shown in FIG. 2. This device, a model AD9000 ADC from Analog Devices, Inc. of Norwood, Massachusetts, achieves 75 MHz word rates. As the block diagram shows, sixty-four parallel comparators 42-1 through 42-64 are employed to digitize fast-moving analog input signals. An overflow bit makes it possible to connect multiple units easily, in parallel, to obtain up to eight bits of digital data at word rates comparable to those achieved by the devices operating independently. Wired-OR logic circuits within the device encode the comparator outputs into a binary format of six bits of parallel data, along with the overflow bit.
The outputs of the comparators 42-i are applied to a corresponding set of latches 44-i controlled by the command signal applied to the ENCODE input at terminal 46. When the ENCODE command is low, the latches 44-i are transparent, establishing the "track" mode. When the ENCODE input changes to high, the latches go into a "hold" or "latched" condition, thus seizing the most recent digital outputs of the comparators and applying them to the encoding circuits. The data held in the latches is converted to binary form by the encoders 48 and 50 and the binary word is applied to the output stages 52 as a six-bit digital representation of the analog signal which was present at the comparator input 54 at the instant the ENCODE command went high.
All-flash ADC's tend to have fairly random linearity errors. The overall linearity in monolithic flash converters is determined primarily by comparator offset voltage matching and tolerance of the resistors comprising the voltage divider. Digital output codes can be missed if the offset voltages of adjacent comparators are of opposite polarities and sufficient magnitude.
The digital code at the output of the comparators in a flash converter is commonly known as "thermometer code." When everything is working ideally, the collection of comparator outputs should be analogous to an analog liquid thermometer tube: all zeroes above the input level, all ones below. The zeroes-to-ones transition point rises and falls with the input level, like the temperature sensed by a thermometer.
The thermometer code is translated to a binary output words by using the zeroes-to-ones transition point to address encoding logic such as read-only memory (ROM). FIG. 3 shows a typical circuit 60 (well-known to those skilled in the art and therefore requiring no detailed explanation) for performing this function. At each of the nodes 64-1, 64-2 and 64-3, a two-input AND function is performed on the two associated inputs from the comparators. Each of nodes 64-i drives a ROM address line 65-i. Each ROM Address line is connected to the base of one or more transistors which drive ROM output lines 62-j. For example, address line 65-1 drives transistors 66a, 66b and 66c. Note that wherever a zero is "to the right" of a one in the inputs 61-i from the comparators, a ROM output line 62-i goes high, impressing a binary code on the output lines. (That is, the circuit looks for a "10" pattern match.) When two or more of transistors 66 have their emitters connected to the same ROM output line, such as transistors 66a and 66d, the wiring together of those emitters creates a wired-OR function; that is, if two ROM lines should go high, the output will be the bit-wise OR of the two ROM outputs. Two ROM lines do sometimes go high, even though under ideal conditions this should not occur. For example, under high-input-slew-rate conditions, timing differences between signal paths or even slight differences in comparator response times can cause the effective strobe point of one comparator to be quite different from its neighbors. Since comparators are usually arranged in several rows, this problem is accentuated at the boundaries between rows, where the signals to adjacent comparators may take vastly different routes and incur concomitantly different propagation delays. Moreover, since row boundaries usually occur at major carry points, the error resulting from OR'ed codes can be substantial.
Examples of code errors of interest appear in FIGS. 4A through 4D, each of which shows a sequence of adjacent comparator outputs 70-i from a corresponding set of electrically adjacent comparators (not shown, but similar to comparators 16-i of FIG. 1) connected to the electrically adjacent taps of a voltage divider (e.g., resistive ladder; not shown) in a flash converter. The outputs 70-i occur at some arbitrary point on the voltage divider. In FIG. 4A, either the logical zero value of the output of comparator 70-2 is in error, or the logical one value of the output of comparator 70-3 is in error. Either way, there is a one-bit error. In FIG. 4B, the zero output of comparator 70-2 is most likely erroneous; of course, there is also a probability that the two ones at the outputs of comparators 70-1 and 70-3 are both in error, instead, but a two-bit error is far less likely than a single-bit error. FIG. 4C shows an example where the one at the output of comparator 70-4 is the most likely error. A two-bit error is shown in FIG. 4D. The two bits at the outputs of comparators 70-1 and 70-2 should both be ones or the two bits at the outputs of comparators 70-3 and 70-4 should both be zeroes, instead of the situation as illustrated. By analogy to a mercury thermometer, the code inconsistencies shown in FIGS. 4A-4D are like "bubbles" in the liquid "mercury" of the thermometer code. Traditionally, such bubbles have been suppressed by using what amounts to a three-input gate to address the ROM. This approach, for example, requires two zeroes and a one to cause the ROM line to go high. Such a technique resolves the errors in FIGS. 4A and 4B, but it does not resolve the errors shown in FIGS. 4C and 4D. A four-input gate would be able to detect and correct more errors, but at the expense of a considerable increase in complexity. Such complexity translates directly to consumption of increased power and integrated circuit area, as well as to an increase in product cost.
The effect of such errors on accuracy of measurement is a second problem. For example, in FIG. 4A, an input gate which requires two zeroes and a one will select position 81 as the top of the thermometer mercury, whereas a gate requiring two ones and a zero will select position 83 instead. A "best guess" correction of the error would probably indicate a position midway between positions 81 and 83 - i.e., position 82.
Accordingly, an object of the present invention is the provision of an improved decoding method and apparatus for "flash" analog-to-digital converters.
Another object of the invention is to provide a converter which provides, on average, a high accuracy error correction.